Digital ASIC Design Engineer

Design, simulation, synthesis, layout of ASIC (Application Specific
Integrated Circuits) from RTL to GDSII. State of the art technologies below
28 nm.

Project description :

Design on 3 technologies 16/20/28 nm the most efficient Bitcoin mining ASIC
on the market accordingly the power consumption W/GH and cost per GH till
01/2015.

- Degree or equivalent in Electronic or Electrical Engineering;
- An established background in ASIC/FPGA design, with an ability to ability
to turn architecture into real hardware;
- Strong knowledge of high speed and low power design;
- VHDL or Verilog RTL coding expertise;
- Prior experience working in the video / graphics domain would be a plus,
but not essential;
- Good interpersonal and communication skills, with ability to lead and motivate the team.

Preferences :
- Knowledge of Cadence Virtuoso design package.

- A stable position in an international company;
- Career opportunities.